Lista rozkazów - tabela: Różnice pomiędzy wersjami

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(→‎Prefix CB)
(→‎Operacje z rejestrem IX)
Linia 926: Linia 926:
  
 
== Operacje z rejestrem IX ==
 
== Operacje z rejestrem IX ==
 +
{|class="wikitable" style="text-align:center"
 +
!scope="col"|\
 +
!scope="col"|x0
 +
!scope="col"|x1
 +
!scope="col"|x2
 +
!scope="col"|x3
 +
!scope="col"|x4
 +
!scope="col"|x5
 +
!scope="col"|x6
 +
!scope="col"|x7
 +
!scope="col"|x8
 +
!scope="col"|x9
 +
!scope="col"|xA
 +
!scope="col"|xB
 +
!scope="col"|xC
 +
!scope="col"|xD
 +
!scope="col"|xE
 +
!scope="col"|xF
 +
|-
 +
!scope="row"|0x
 +
|[[Rozkaz NOP|nop]]
 +
|[[Rozkazy przesłań 16-bitowe|ld bc,NN ]]
 +
|[[Rozkazy przesłań 8-bitowe|ld (bc),a]]
 +
|[[Rozkaz |inc bc]]
 +
|[[Rozkaz |inc b]]
 +
|[[Rozkaz |dec b]]
 +
|[[Rozkaz |ld b,N]]
 +
|[[Rozkaz |rlc a]]
 +
|[[Rozkaz |ex af,af']]
 +
|[[Rozkaz |add hl,bc]]
 +
|[[Rozkaz |ld a,(bc)]]
 +
|[[Rozkaz |dec bc]]
 +
|[[Rozkaz |inc c]]
 +
|[[Rozkaz |dec c]]
 +
|[[Rozkaz |ld c,N]]
 +
|[[Rozkaz |rrc a]]
 +
|-
 +
!scope="row"|1x
 +
|[[Rozkaz |djnz X]]
 +
|[[Rozkaz |ld de,NN]]
 +
|[[Rozkaz |ld (de),a]]
 +
|[[Rozkaz |inc de]]
 +
|[[Rozkaz |inc d]]
 +
|[[Rozkaz |dec d]]
 +
|[[Rozkaz |ld d,N]]
 +
|[[Rozkaz |rla]]
 +
|[[Rozkaz |jr X]]
 +
|[[Rozkaz |add hl,de]]
 +
|[[Rozkaz |ld a,(de)]]
 +
|[[Rozkaz |dec de]]
 +
|[[Rozkaz |inc e]]
 +
|[[Rozkaz |dec e]]
 +
|[[Rozkaz |ld e,N]]
 +
|[[Rozkaz |rra]]
 +
|-
 +
!scope="row"|2x
 +
|[[Rozkaz |jr nz,X]]
 +
|[[Rozkaz |ld hl,NN]]
 +
|[[Rozkaz |ld (NN),hl]]
 +
|[[Rozkaz |inc hl]]
 +
|[[Rozkaz |inc h]]
 +
|[[Rozkaz |dec h]]
 +
|[[Rozkaz |ld h,N]]
 +
|[[Rozkaz |daa]]
 +
|[[Rozkaz |jr z,X]]
 +
|[[Rozkaz |add hl,hl]]
 +
|[[Rozkaz |ld hl,(NN)]]
 +
|[[Rozkaz |dec hl]]
 +
|[[Rozkaz |inc l]]
 +
|[[Rozkaz |dec l]]
 +
|[[Rozkaz |ld l,N]]
 +
|[[Rozkaz |cpl]]
 +
|-
 +
!scope="row"|3x
 +
|[[Rozkaz |jr nc,X]]
 +
|[[Rozkaz |ld sp,NN]]
 +
|[[Rozkaz |ld (NN),a]]
 +
|[[Rozkaz |inc sp]]
 +
|[[Rozkaz |inc (hl)]]
 +
|[[Rozkaz |dec (hl)]]
 +
|[[Rozkaz |ld (hl),N]]
 +
|[[Rozkaz |scf]]
 +
|[[Rozkaz |jr c,X]]
 +
|[[Rozkaz |add hl,sp]]
 +
|[[Rozkaz |ld a,(NN)]]
 +
|[[Rozkaz |dec sp]]
 +
|[[Rozkaz |inc a]]
 +
|[[Rozkaz |dec a]]
 +
|[[Rozkaz |ld a,N]]
 +
|[[Rozkaz |ccf]]
 +
|-
 +
!scope="row"|4x
 +
|[[Rozkaz |ld b,b]]
 +
|[[Rozkaz |ld b,c]]
 +
|[[Rozkaz |ld b,d]]
 +
|[[Rozkaz |ld b,e]]
 +
|[[Rozkaz |ld b,h]]
 +
|[[Rozkaz |ld b,l]]
 +
|[[Rozkaz |ld b,(hl)]]
 +
|[[Rozkaz |ld b,a]]
 +
|[[Rozkaz |ld c,b]]
 +
|[[Rozkaz |ld c,c]]
 +
|[[Rozkaz |ld c,d]]
 +
|[[Rozkaz |ld c,e]]
 +
|[[Rozkaz |ld c,h]]
 +
|[[Rozkaz |ld c,l]]
 +
|[[Rozkaz |ld c,(hl)]]
 +
|[[Rozkaz |ld c,a]]
 +
|-
 +
!scope="row"|5x
 +
|[[Rozkaz |ld d,b]]
 +
|[[Rozkaz |ld d,c]]
 +
|[[Rozkaz |ld d,d]]
 +
|[[Rozkaz |ld d,e]]
 +
|[[Rozkaz |ld d,h]]
 +
|[[Rozkaz |ld d,l]]
 +
|[[Rozkaz |ld d,(hl)]]
 +
|[[Rozkaz |ld d,a]]
 +
|[[Rozkaz |ld e,b]]
 +
|[[Rozkaz |ld e,c]]
 +
|[[Rozkaz |ld e,d]]
 +
|[[Rozkaz |ld e,e]]
 +
|[[Rozkaz |ld e,h]]
 +
|[[Rozkaz |ld e,l]]
 +
|[[Rozkaz |ld e,(hl)]]
 +
|[[Rozkaz |ld e,a]]
 +
|-
 +
!scope="row"|6x
 +
|[[Rozkaz |ld h,b]]
 +
|[[Rozkaz |ld h,c]]
 +
|[[Rozkaz |ld h,d]]
 +
|[[Rozkaz |ld h,e]]
 +
|[[Rozkaz |ld h,h]]
 +
|[[Rozkaz |ld h,l]]
 +
|[[Rozkaz |ld h,(hl)]]
 +
|[[Rozkaz |ld h,a]]
 +
|[[Rozkaz |ld l,b]]
 +
|[[Rozkaz |ld l,c]]
 +
|[[Rozkaz |ld l,d]]
 +
|[[Rozkaz |ld l,e]]
 +
|[[Rozkaz |ld l,h]]
 +
|[[Rozkaz |ld l,l]]
 +
|[[Rozkaz |ld l,(hl)]]
 +
|[[Rozkaz |ld l,a]]
 +
|-
 +
!scope="row"|7x
 +
|[[Rozkaz |ld (hl),b]]
 +
|[[Rozkaz |ld (hl),c]]
 +
|[[Rozkaz |ld (hl),d]]
 +
|[[Rozkaz |ld (hl),e]]
 +
|[[Rozkaz |ld (hl),h]]
 +
|[[Rozkaz |ld (hl),l]]
 +
|[[Rozkaz |halt]]
 +
|[[Rozkaz |ld (hl),a]]
 +
|[[Rozkaz |ld a,b]]
 +
|[[Rozkaz |ld a,c]]
 +
|[[Rozkaz |ld a,d]]
 +
|[[Rozkaz |ld a,e]]
 +
|[[Rozkaz |ld a,h]]
 +
|[[Rozkaz |ld a,l]]
 +
|[[Rozkaz |ld a,(hl)]]
 +
|[[Rozkaz |ld a,a]]
 +
|-
 +
!scope="row"|8x
 +
|[[Rozkaz |add a,b]]
 +
|[[Rozkaz |add a,c]]
 +
|[[Rozkaz |add a,d]]
 +
|[[Rozkaz |add a,e]]
 +
|[[Rozkaz |add a,h]]
 +
|[[Rozkaz |add a,l]]
 +
|[[Rozkaz |add a,(hl)]]
 +
|[[Rozkaz |add a,a]]
 +
|[[Rozkaz |adc a,b]]
 +
|[[Rozkaz |adc a,c]]
 +
|[[Rozkaz |adc a,d]]
 +
|[[Rozkaz |adc a,e]]
 +
|[[Rozkaz |adc a,h]]
 +
|[[Rozkaz |adc a,l]]
 +
|[[Rozkaz |adc a,(hl)]]
 +
|[[Rozkaz |adc a,a]]
 +
|-
 +
!scope="row"|9x
 +
|[[Rozkaz |sub b]]
 +
|[[Rozkaz |sub c]]
 +
|[[Rozkaz |sub d]]
 +
|[[Rozkaz |sub e]]
 +
|[[Rozkaz |sub h]]
 +
|[[Rozkaz |sub l]]
 +
|[[Rozkaz |sub (hl)]]
 +
|[[Rozkaz |sub a]]
 +
|[[Rozkaz |sbc a,b]]
 +
|[[Rozkaz |sbc a,c]]
 +
|[[Rozkaz |sbc a,d]]
 +
|[[Rozkaz |sbc a,e]]
 +
|[[Rozkaz |sbc a,h]]
 +
|[[Rozkaz |sbc a,l]]
 +
|[[Rozkaz |sbc a,(hl)]]
 +
|[[Rozkaz |sbc a,a]]
 +
|-
 +
!scope="row"|Ax
 +
|[[Rozkaz |and b]]
 +
|[[Rozkaz |and c]]
 +
|[[Rozkaz |and d]]
 +
|[[Rozkaz |and e]]
 +
|[[Rozkaz |and h]]
 +
|[[Rozkaz |and l]]
 +
|[[Rozkaz |and (hl)]]
 +
|[[Rozkaz |and a]]
 +
|[[Rozkaz |xor b]]
 +
|[[Rozkaz |xor c]]
 +
|[[Rozkaz |xor d]]
 +
|[[Rozkaz |xor e]]
 +
|[[Rozkaz |xor h]]
 +
|[[Rozkaz |xor l]]
 +
|[[Rozkaz |xor (hl)]]
 +
|[[Rozkaz |xor a]]
 +
|-
 +
!scope="row"|Bx
 +
|[[Rozkaz |or b]]
 +
|[[Rozkaz |or c]]
 +
|[[Rozkaz |or d]]
 +
|[[Rozkaz |or e]]
 +
|[[Rozkaz |or h]]
 +
|[[Rozkaz |or l]]
 +
|[[Rozkaz |or (hl)]]
 +
|[[Rozkaz |or a]]
 +
|[[Rozkaz |cp b]]
 +
|[[Rozkaz |cp c]]
 +
|[[Rozkaz |cp d]]
 +
|[[Rozkaz |cp e]]
 +
|[[Rozkaz |cp h]]
 +
|[[Rozkaz |cp l]]
 +
|[[Rozkaz |cp (hl)]]
 +
|[[Rozkaz |cp a]]
 +
|-
 +
!scope="row"|Cx
 +
|[[Rozkaz |ret nz]]
 +
|[[Rozkaz |pop bc]]
 +
|[[Rozkaz |jp nz,NN]]
 +
|[[Rozkaz |jp NN]]
 +
|[[Rozkaz |call nz,NN]]
 +
|[[Rozkaz |push bc]]
 +
|[[Rozkaz |add a,N]]
 +
|[[Rozkaz |rst 0]]
 +
|[[Rozkaz |ret z]]
 +
|[[Rozkaz |ret]]
 +
|[[Rozkaz |jp z,NN]]
 +
|<b>[[#Prefix DDCB|prefix DDCB]]</b>
 +
|[[Rozkaz |call z,NN]]
 +
|[[Rozkaz |call NN]]
 +
|[[Rozkaz |adc a,N]]
 +
|[[Rozkaz |rst 8]]
 +
|-
 +
!scope="row"|Dx
 +
|[[Rozkaz |ret nc]]
 +
|[[Rozkaz |pop de]]
 +
|[[Rozkaz |jp nc,NN]]
 +
|[[Rozkaz |out (N),a]]
 +
|[[Rozkaz |call nc,NN]]
 +
|[[Rozkaz |push de]]
 +
|[[Rozkaz |sub N]]
 +
|[[Rozkaz |rst 16]]
 +
|[[Rozkaz |ret c]]
 +
|[[Rozkaz |exx]]
 +
|[[Rozkaz |jp c,NN]]
 +
|[[Rozkaz |in a,(N)]]
 +
|[[Rozkaz |call c,NN]]
 +
|&nbsp;
 +
|[[Rozkaz |sbc a,N]]
 +
|[[Rozkaz |rst 24]]
 +
|-
 +
!scope="row"|Ex
 +
|[[Rozkaz |ret po]]
 +
|[[Rozkaz |pop hl]]
 +
|[[Rozkaz |jp po,NN]]
 +
|[[Rozkaz |ex (sp),hl]]
 +
|[[Rozkaz |call po,NN]]
 +
|[[Rozkaz |push hl]]
 +
|[[Rozkaz |and N]]
 +
|[[Rozkaz |rst 32]]
 +
|[[Rozkaz |ret pe]]
 +
|[[Rozkaz |jp (hl)]]
 +
|[[Rozkaz |jp pe,NN]]
 +
|[[Rozkaz |ex de,hl]]
 +
|[[Rozkaz |call pe,NN]]
 +
|<b>[[#Prefix DDED|prefix DDED]]</b>
 +
|[[Rozkaz |xor N]]
 +
|[[Rozkaz |rst 40]]
 +
|-
 +
!scope="row"|Fx
 +
|[[Rozkaz |ret p]]
 +
|[[Rozkaz |pop af]]
 +
|[[Rozkaz |jp p,NN]]
 +
|[[Rozkaz |di]]
 +
|[[Rozkaz |call p,NN]]
 +
|[[Rozkaz |push af]]
 +
|[[Rozkaz |or N]]
 +
|[[Rozkaz |rst 48]]
 +
|[[Rozkaz |ret m]]
 +
|[[Rozkaz |ld sp,hl]]
 +
|[[Rozkaz |jp m,NN]]
 +
|[[Rozkaz |ei]]
 +
|[[Rozkaz |call m,NN]]
 +
|&nbsp;
 +
|[[Rozkaz |cp N]]
 +
|[[Rozkaz |rst 56]]
 +
|}
 +
== Prefix DDCB ==
 +
{|class="wikitable" style="text-align:center"
 +
!scope="col"|\
 +
!scope="col"|x0
 +
!scope="col"|x1
 +
!scope="col"|x2
 +
!scope="col"|x3
 +
!scope="col"|x4
 +
!scope="col"|x5
 +
!scope="col"|x6
 +
!scope="col"|x7
 +
!scope="col"|x8
 +
!scope="col"|x9
 +
!scope="col"|xA
 +
!scope="col"|xB
 +
!scope="col"|xC
 +
!scope="col"|xD
 +
!scope="col"|xE
 +
!scope="col"|xF
 +
|-
 +
!scope="row"|0x
 +
|[[Rozkaz |rlc b]]
 +
|[[Rozkaz |rlc c]]
 +
|[[Rozkaz |rlc d]]
 +
|[[Rozkaz |rlc e]]
 +
|[[Rozkaz |rlc h]]
 +
|[[Rozkaz |rlc l]]
 +
|[[Rozkaz |rlc (hl)]]
 +
|[[Rozkaz |rlc a]]
 +
|[[Rozkaz |rrc b]]
 +
|[[Rozkaz |rrc c]]
 +
|[[Rozkaz |rrc d]]
 +
|[[Rozkaz |rrc e]]
 +
|[[Rozkaz |rrc h]]
 +
|[[Rozkaz |rrc l]]
 +
|[[Rozkaz |rrc (hl)]]
 +
|[[Rozkaz |rrc a]]
 +
|-
 +
!scope="row"|1x
 +
|[[Rozkaz |rl b]]
 +
|[[Rozkaz |rl c]]
 +
|[[Rozkaz |rl d]]
 +
|[[Rozkaz |rl e]]
 +
|[[Rozkaz |rl h]]
 +
|[[Rozkaz |rl l]]
 +
|[[Rozkaz |rl (hl)]]
 +
|[[Rozkaz |rl a]]
 +
|[[Rozkaz |rr b]]
 +
|[[Rozkaz |rr c]]
 +
|[[Rozkaz |rr d]]
 +
|[[Rozkaz |rr e]]
 +
|[[Rozkaz |rr h]]
 +
|[[Rozkaz |rr l]]
 +
|[[Rozkaz |rr (hl)]]
 +
|[[Rozkaz |rr a]]
 +
|-
 +
!scope="row"|2x
 +
|[[Rozkaz |sla b]]
 +
|[[Rozkaz |sla c]]
 +
|[[Rozkaz |sla d]]
 +
|[[Rozkaz |sla e]]
 +
|[[Rozkaz |sla h]]
 +
|[[Rozkaz |sla l]]
 +
|[[Rozkaz |sla (hl)]]
 +
|[[Rozkaz |sla a]]
 +
|[[Rozkaz |sra b]]
 +
|[[Rozkaz |sra c]]
 +
|[[Rozkaz |sra d]]
 +
|[[Rozkaz |sra e]]
 +
|[[Rozkaz |sra h]]
 +
|[[Rozkaz |sra l]]
 +
|[[Rozkaz |sra (hl)]]
 +
|[[Rozkaz |sra a]]
 +
|-
 +
!scope="row"|3x
 +
|<i>sll b</i>
 +
|<i>sll c</i>
 +
|<i>sll d</i>
 +
|<i>sll e</i>
 +
|<i>sll h</i>
 +
|<i>sll l</i>
 +
|<i>sll (hl)</i>
 +
|<i>sll a</i>
 +
|[[Rozkaz |srl b]]
 +
|[[Rozkaz |srl c]]
 +
|[[Rozkaz |srl d]]
 +
|[[Rozkaz |srl e]]
 +
|[[Rozkaz |srl h]]
 +
|[[Rozkaz |srl l]]
 +
|[[Rozkaz |srl (hl)]]
 +
|[[Rozkaz |srl a]]
 +
|-
 +
!scope="row"|4x
 +
|[[Rozkaz |bit 0,b]]
 +
|[[Rozkaz |bit 0,c]]
 +
|[[Rozkaz |bit 0,d]]
 +
|[[Rozkaz |bit 0,e]]
 +
|[[Rozkaz |bit 0,h]]
 +
|[[Rozkaz |bit 0,l]]
 +
|[[Rozkaz |bit 0,(hl)]]
 +
|[[Rozkaz |bit 0,a]]
 +
|[[Rozkaz |bit 1,b]]
 +
|[[Rozkaz |bit 1,c]]
 +
|[[Rozkaz |bit 1,d]]
 +
|[[Rozkaz |bit 1,e]]
 +
|[[Rozkaz |bit 1,h]]
 +
|[[Rozkaz |bit 1,l]]
 +
|[[Rozkaz |bit 1,(hl)]]
 +
|[[Rozkaz |bit 1,a]]
 +
|-
 +
!scope="row"|5x
 +
|[[Rozkaz |bit 2,b]]
 +
|[[Rozkaz |bit 2,c]]
 +
|[[Rozkaz |bit 2,d]]
 +
|[[Rozkaz |bit 2,e]]
 +
|[[Rozkaz |bit 2,h]]
 +
|[[Rozkaz |bit 2,l]]
 +
|[[Rozkaz |bit 2,(hl)]]
 +
|[[Rozkaz |bit 2,a]]
 +
|[[Rozkaz |bit 3,b]]
 +
|[[Rozkaz |bit 3,c]]
 +
|[[Rozkaz |bit 3,d]]
 +
|[[Rozkaz |bit 3,e]]
 +
|[[Rozkaz |bit 3,h]]
 +
|[[Rozkaz |bit 3,l]]
 +
|[[Rozkaz |bit 3,(hl)]]
 +
|[[Rozkaz |bit 3,a]]
 +
|-
 +
!scope="row"|6x
 +
|[[Rozkaz |bit 4,b]]
 +
|[[Rozkaz |bit 4,c]]
 +
|[[Rozkaz |bit 4,d]]
 +
|[[Rozkaz |bit 4,e]]
 +
|[[Rozkaz |bit 4,h]]
 +
|[[Rozkaz |bit 4,l]]
 +
|[[Rozkaz |bit 4,(hl)]]
 +
|[[Rozkaz |bit 4,a]]
 +
|[[Rozkaz |bit 5,b]]
 +
|[[Rozkaz |bit 5,c]]
 +
|[[Rozkaz |bit 5,d]]
 +
|[[Rozkaz |bit 5,e]]
 +
|[[Rozkaz |bit 5,h]]
 +
|[[Rozkaz |bit 5,l]]
 +
|[[Rozkaz |bit 5,(hl)]]
 +
|[[Rozkaz |bit 5,a]]
 +
|-
 +
!scope="row"|7x
 +
|[[Rozkaz |bit 6,b]]
 +
|[[Rozkaz |bit 6,c]]
 +
|[[Rozkaz |bit 6,d]]
 +
|[[Rozkaz |bit 6,e]]
 +
|[[Rozkaz |bit 6,h]]
 +
|[[Rozkaz |bit 6,l]]
 +
|[[Rozkaz |bit 6,(hl)]]
 +
|[[Rozkaz |bit 6,a]]
 +
|[[Rozkaz |bit 7,b]]
 +
|[[Rozkaz |bit 7,c]]
 +
|[[Rozkaz |bit 7,d]]
 +
|[[Rozkaz |bit 7,e]]
 +
|[[Rozkaz |bit 7,h]]
 +
|[[Rozkaz |bit 7,l]]
 +
|[[Rozkaz |bit 7,(hl)]]
 +
|[[Rozkaz |bit 7,a]]
 +
|-
 +
!scope="row"|8x
 +
|[[Rozkaz |res 0,b]]
 +
|[[Rozkaz |res 0,c]]
 +
|[[Rozkaz |res 0,d]]
 +
|[[Rozkaz |res 0,e]]
 +
|[[Rozkaz |res 0,h]]
 +
|[[Rozkaz |res 0,l]]
 +
|[[Rozkaz |res 0,(hl)]]
 +
|[[Rozkaz |res 0,a]]
 +
|[[Rozkaz |res 1,b]]
 +
|[[Rozkaz |res 1,c]]
 +
|[[Rozkaz |res 1,d]]
 +
|[[Rozkaz |res 1,e]]
 +
|[[Rozkaz |res 1,h]]
 +
|[[Rozkaz |res 1,l]]
 +
|[[Rozkaz |res 1,(hl)]]
 +
|[[Rozkaz |res 1,a]]
 +
|-
 +
!scope="row"|9x
 +
|[[Rozkaz |res 2,b]]
 +
|[[Rozkaz |res 2,c]]
 +
|[[Rozkaz |res 2,d]]
 +
|[[Rozkaz |res 2,e]]
 +
|[[Rozkaz |res 2,h]]
 +
|[[Rozkaz |res 2,l]]
 +
|[[Rozkaz |res 2,(hl)]]
 +
|[[Rozkaz |res 2,a]]
 +
|[[Rozkaz |res 3,b]]
 +
|[[Rozkaz |res 3,c]]
 +
|[[Rozkaz |res 3,d]]
 +
|[[Rozkaz |res 3,e]]
 +
|[[Rozkaz |res 3,h]]
 +
|[[Rozkaz |res 3,l]]
 +
|[[Rozkaz |res 3,(hl)]]
 +
|[[Rozkaz |res 3,a]]
 +
|-
 +
!scope="row"|Ax
 +
|[[Rozkaz |res 4,b]]
 +
|[[Rozkaz |res 4,c]]
 +
|[[Rozkaz |res 4,d]]
 +
|[[Rozkaz |res 4,e]]
 +
|[[Rozkaz |res 4,h]]
 +
|[[Rozkaz |res 4,l]]
 +
|[[Rozkaz |res 4,(hl)]]
 +
|[[Rozkaz |res 4,a]]
 +
|[[Rozkaz |res 5,b]]
 +
|[[Rozkaz |res 5,c]]
 +
|[[Rozkaz |res 5,d]]
 +
|[[Rozkaz |res 5,e]]
 +
|[[Rozkaz |res 5,h]]
 +
|[[Rozkaz |res 5,l]]
 +
|[[Rozkaz |res 5,(hl)]]
 +
|[[Rozkaz |res 5,a]]
 +
|-
 +
!scope="row"|Bx
 +
|[[Rozkaz |res 6,b]]
 +
|[[Rozkaz |res 6,c]]
 +
|[[Rozkaz |res 6,d]]
 +
|[[Rozkaz |res 6,e]]
 +
|[[Rozkaz |res 6,h]]
 +
|[[Rozkaz |res 6,l]]
 +
|[[Rozkaz |res 6,(hl)]]
 +
|[[Rozkaz |res 6,a]]
 +
|[[Rozkaz |res 7,b]]
 +
|[[Rozkaz |res 7,c]]
 +
|[[Rozkaz |res 7,d]]
 +
|[[Rozkaz |res 7,e]]
 +
|[[Rozkaz |res 7,h]]
 +
|[[Rozkaz |res 7,l]]
 +
|[[Rozkaz |res 7,(hl)]]
 +
|[[Rozkaz |res 7,a]]
 +
|-
 +
!scope="row"|Cx
 +
|[[Rozkaz |set 0,b]]
 +
|[[Rozkaz |set 0,c]]
 +
|[[Rozkaz |set 0,d]]
 +
|[[Rozkaz |set 0,e]]
 +
|[[Rozkaz |set 0,h]]
 +
|[[Rozkaz |set 0,l]]
 +
|[[Rozkaz |set 0,(hl)]]
 +
|[[Rozkaz |set 0,a]]
 +
|[[Rozkaz |set 1,b]]
 +
|[[Rozkaz |set 1,c]]
 +
|[[Rozkaz |set 1,d]]
 +
|[[Rozkaz |set 1,e]]
 +
|[[Rozkaz |set 1,h]]
 +
|[[Rozkaz |set 1,l]]
 +
|[[Rozkaz |set 1,(hl)]]
 +
|[[Rozkaz |set 1,a]]
 +
|-
 +
!scope="row"|Dx
 +
|[[Rozkaz |set 2,b]]
 +
|[[Rozkaz |set 2,c]]
 +
|[[Rozkaz |set 2,d]]
 +
|[[Rozkaz |set 2,e]]
 +
|[[Rozkaz |set 2,h]]
 +
|[[Rozkaz |set 2,l]]
 +
|[[Rozkaz |set 2,(hl)]]
 +
|[[Rozkaz |set 2,a]]
 +
|[[Rozkaz |set 3,b]]
 +
|[[Rozkaz |set 3,c]]
 +
|[[Rozkaz |set 3,d]]
 +
|[[Rozkaz |set 3,e]]
 +
|[[Rozkaz |set 3,h]]
 +
|[[Rozkaz |set 3,l]]
 +
|[[Rozkaz |set 3,(hl)]]
 +
|[[Rozkaz |set 3,a]]
 +
|-
 +
!scope="row"|Ex
 +
|[[Rozkaz |set 4,b]]
 +
|[[Rozkaz |set 4,c]]
 +
|[[Rozkaz |set 4,d]]
 +
|[[Rozkaz |set 4,e]]
 +
|[[Rozkaz |set 4,h]]
 +
|[[Rozkaz |set 4,l]]
 +
|[[Rozkaz |set 4,(hl)]]
 +
|[[Rozkaz |set 4,a]]
 +
|[[Rozkaz |set 5,b]]
 +
|[[Rozkaz |set 5,c]]
 +
|[[Rozkaz |set 5,d]]
 +
|[[Rozkaz |set 5,e]]
 +
|[[Rozkaz |set 5,h]]
 +
|[[Rozkaz |set 5,l]]
 +
|[[Rozkaz |set 5,(hl)]]
 +
|[[Rozkaz |set 5,a]]
 +
|-
 +
!scope="row"|Fx
 +
|[[Rozkaz |set 6,b]]
 +
|[[Rozkaz |set 6,c]]
 +
|[[Rozkaz |set 6,d]]
 +
|[[Rozkaz |set 6,e]]
 +
|[[Rozkaz |set 6,h]]
 +
|[[Rozkaz |set 6,l]]
 +
|[[Rozkaz |set 6,(hl)]]
 +
|[[Rozkaz |set 6,a]]
 +
|[[Rozkaz |set 7,b]]
 +
|[[Rozkaz |set 7,c]]
 +
|[[Rozkaz |set 7,d]]
 +
|[[Rozkaz |set 7,e]]
 +
|[[Rozkaz |set 7,h]]
 +
|[[Rozkaz |set 7,l]]
 +
|[[Rozkaz |set 7,(hl)]]
 +
|[[Rozkaz |set 7,a]]
 +
|}
 +
== Prefix DDED ==
 +
{|class="wikitable" style="text-align:center"
 +
!scope="col"|\
 +
!scope="col"|x0
 +
!scope="col"|x1
 +
!scope="col"|x2
 +
!scope="col"|x3
 +
!scope="col"|x4
 +
!scope="col"|x5
 +
!scope="col"|x6
 +
!scope="col"|x7
 +
!scope="col"|x8
 +
!scope="col"|x9
 +
!scope="col"|xA
 +
!scope="col"|xB
 +
!scope="col"|xC
 +
!scope="col"|xD
 +
!scope="col"|xE
 +
!scope="col"|xF
 +
|-
 +
!scope="row"|0x
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|-
 +
!scope="row"|1x
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|-
 +
!scope="row"|2x
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|-
 +
!scope="row"|3x
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|-
 +
!scope="row"|4x
 +
|[[Rozkaz |in b,(c)]]
 +
|[[Rozkaz |out (c),b]]
 +
|[[Rozkaz |sbc hl,bc]]
 +
|[[Rozkaz |ld (NN),bc]]
 +
|[[Rozkaz |neg]]
 +
|[[Rozkaz |retn]]
 +
|[[Rozkaz |im 0]]
 +
|[[Rozkaz |ld i,a]]
 +
|[[Rozkaz |in c,(c)]]
 +
|[[Rozkaz |out (c),c]]
 +
|[[Rozkaz |adc hl,bc]]
 +
|[[Rozkaz |ld bc,(NN)]]
 +
|&nbsp;
 +
|[[Rozkaz |reti]]
 +
|&nbsp;
 +
|[[Rozkaz |ld r,a]]
 +
|-
 +
!scope="row"|5x
 +
|[[Rozkaz |in d,(c)]]
 +
|[[Rozkaz |out (c),d]]
 +
|[[Rozkaz |sbc hl,de]]
 +
|[[Rozkaz |ld (NN),de]]
 +
|&nbsp;
 +
|&nbsp;
 +
|[[Rozkaz |im 1]]
 +
|[[Rozkaz |ld a,i]]
 +
|[[Rozkaz |in e,(c)]]
 +
|[[Rozkaz |out (c),e]]
 +
|[[Rozkaz |adc hl,de]]
 +
|[[Rozkaz |ld de,(NN)]]
 +
|&nbsp;
 +
|&nbsp;
 +
|[[Rozkaz |im 2]]
 +
|[[Rozkaz |ld a,r]]
 +
|-
 +
!scope="row"|6x
 +
|[[Rozkaz |in h,(c)]]
 +
|[[Rozkaz |out (c),h]]
 +
|[[Rozkaz |sbc hl,hl]]
 +
|[[Rozkaz |ld (NN),hl]]
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|[[Rozkaz |rrd]]
 +
|[[Rozkaz |in l,(c)]]
 +
|[[Rozkaz |out (c),l]]
 +
|[[Rozkaz |adc hl,hl]]
 +
|[[Rozkaz |ld hl,(NN)]]
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|[[Rozkaz |rld]]
 +
|-
 +
!scope="row"|7x
 +
|[[Rozkaz |in f,(c)]]
 +
|<i>out (c),f</i>
 +
|[[Rozkaz |sbc hl,sp]]
 +
|[[Rozkaz |ld (NN),sp]]
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|[[Rozkaz |in a,(c)]]
 +
|[[Rozkaz |out (c),a]]
 +
|[[Rozkaz |adc hl,sp]]
 +
|[[Rozkaz |ld sp,(NN)]]
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|-
 +
!scope="row"|8x
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|-
 +
!scope="row"|9x
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|-
 +
!scope="row"|Ax
 +
|[[Rozkaz |ldi]]
 +
|[[Rozkaz |cpi]]
 +
|[[Rozkaz |ini]]
 +
|[[Rozkaz |outi]]
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|[[Rozkaz |ldd]]
 +
|[[Rozkaz |cpd]]
 +
|[[Rozkaz |ind]]
 +
|[[Rozkaz |outd]]
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|-
 +
!scope="row"|Bx
 +
|[[Rozkaz |ldir]]
 +
|[[Rozkaz |cpir]]
 +
|[[Rozkaz |inir]]
 +
|[[Rozkaz |otir]]
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|[[Rozkaz |lddr]]
 +
|[[Rozkaz |cpdr]]
 +
|[[Rozkaz |indr]]
 +
|[[Rozkaz |otdr]]
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|-
 +
!scope="row"|Cx
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|-
 +
!scope="row"|Dx
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|-
 +
!scope="row"|Ex
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|-
 +
!scope="row"|Fx
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|&nbsp;
 +
|}
 +
 
== Operacje z rejestrem IY ==
 
== Operacje z rejestrem IY ==

Wersja z 10:31, 30 maj 2014

Podstawowe

\ x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE xF
0x nop ld bc,NN ld (bc),a inc bc inc b dec b ld b,N rlc a ex af,af' add hl,bc ld a,(bc) dec bc inc c dec c ld c,N rrc a
1x djnz X ld de,NN ld (de),a inc de inc d dec d ld d,N rla jr X add hl,de ld a,(de) dec de inc e dec e ld e,N rra
2x jr nz,X ld hl,NN ld (NN),hl inc hl inc h dec h ld h,N daa jr z,X add hl,hl ld hl,(NN) dec hl inc l dec l ld l,N cpl
3x jr nc,X ld sp,NN ld (NN),a inc sp inc (hl) dec (hl) ld (hl),N scf jr c,X add hl,sp ld a,(NN) dec sp inc a dec a ld a,N ccf
4x ld b,b ld b,c ld b,d ld b,e ld b,h ld b,l ld b,(hl) ld b,a ld c,b ld c,c ld c,d ld c,e ld c,h ld c,l ld c,(hl) ld c,a
5x ld d,b ld d,c ld d,d ld d,e ld d,h ld d,l ld d,(hl) ld d,a ld e,b ld e,c ld e,d ld e,e ld e,h ld e,l ld e,(hl) ld e,a
6x ld h,b ld h,c ld h,d ld h,e ld h,h ld h,l ld h,(hl) ld h,a ld l,b ld l,c ld l,d ld l,e ld l,h ld l,l ld l,(hl) ld l,a
7x ld (hl),b ld (hl),c ld (hl),d ld (hl),e ld (hl),h ld (hl),l halt ld (hl),a ld a,b ld a,c ld a,d ld a,e ld a,h ld a,l ld a,(hl) ld a,a
8x add a,b add a,c add a,d add a,e add a,h add a,l add a,(hl) add a,a adc a,b adc a,c adc a,d adc a,e adc a,h adc a,l adc a,(hl) adc a,a
9x sub b sub c sub d sub e sub h sub l sub (hl) sub a sbc a,b sbc a,c sbc a,d sbc a,e sbc a,h sbc a,l sbc a,(hl) sbc a,a
Ax and b and c and d and e and h and l and (hl) and a xor b xor c xor d xor e xor h xor l xor (hl) xor a
Bx or b or c or d or e or h or l or (hl) or a cp b cp c cp d cp e cp h cp l cp (hl) cp a
Cx ret nz pop bc jp nz,NN jp NN call nz,NN push bc add a,N rst 0 ret z ret jp z,NN prefix CB call z,NN call NN adc a,N rst 8
Dx ret nc pop de jp nc,NN out (N),a call nc,NN push de sub N rst 16 ret c exx jp c,NN in a,(N) call c,NN prefix DD sbc a,N rst 24
Ex ret po pop hl jp po,NN ex (sp),hl call po,NN push hl and N rst 32 ret pe jp (hl) jp pe,NN ex de,hl call pe,NN prefix ED xor N rst 40
Fx ret p pop af jp p,NN di call p,NN push af or N rst 48 ret m ld sp,hl jp m,NN ei call m,NN prefix FD cp N rst 56

Prefix ED

\ x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE xF
0x                                
1x                                
2x                                
3x                                
4x in b,(c) out (c),b sbc hl,bc ld (NN),bc neg retn im 0 ld i,a in c,(c) out (c),c adc hl,bc ld bc,(NN)   reti   ld r,a
5x in d,(c) out (c),d sbc hl,de ld (NN),de     im 1 ld a,i in e,(c) out (c),e adc hl,de ld de,(NN)     im 2 ld a,r
6x in h,(c) out (c),h sbc hl,hl ld (NN),hl       rrd in l,(c) out (c),l adc hl,hl ld hl,(NN)       rld
7x in f,(c) out (c),f sbc hl,sp ld (NN),sp         in a,(c) out (c),a adc hl,sp ld sp,(NN)        
8x                                
9x                                
Ax ldi cpi ini outi         ldd cpd ind outd        
Bx ldir cpir inir otir         lddr cpdr indr otdr        
Cx                                
Dx                                
Ex                                
Fx                                

Prefix CB

\ x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE xF
0x rlc b rlc c rlc d rlc e rlc h rlc l rlc (hl) rlc a rrc b rrc c rrc d rrc e rrc h rrc l rrc (hl) rrc a
1x rl b rl c rl d rl e rl h rl l rl (hl) rl a rr b rr c rr d rr e rr h rr l rr (hl) rr a
2x sla b sla c sla d sla e sla h sla l sla (hl) sla a sra b sra c sra d sra e sra h sra l sra (hl) sra a
3x sll b sll c sll d sll e sll h sll l sll (hl) sll a srl b srl c srl d srl e srl h srl l srl (hl) srl a
4x bit 0,b bit 0,c bit 0,d bit 0,e bit 0,h bit 0,l bit 0,(hl) bit 0,a bit 1,b bit 1,c bit 1,d bit 1,e bit 1,h bit 1,l bit 1,(hl) bit 1,a
5x bit 2,b bit 2,c bit 2,d bit 2,e bit 2,h bit 2,l bit 2,(hl) bit 2,a bit 3,b bit 3,c bit 3,d bit 3,e bit 3,h bit 3,l bit 3,(hl) bit 3,a
6x bit 4,b bit 4,c bit 4,d bit 4,e bit 4,h bit 4,l bit 4,(hl) bit 4,a bit 5,b bit 5,c bit 5,d bit 5,e bit 5,h bit 5,l bit 5,(hl) bit 5,a
7x bit 6,b bit 6,c bit 6,d bit 6,e bit 6,h bit 6,l bit 6,(hl) bit 6,a bit 7,b bit 7,c bit 7,d bit 7,e bit 7,h bit 7,l bit 7,(hl) bit 7,a
8x res 0,b res 0,c res 0,d res 0,e res 0,h res 0,l res 0,(hl) res 0,a res 1,b res 1,c res 1,d res 1,e res 1,h res 1,l res 1,(hl) res 1,a
9x res 2,b res 2,c res 2,d res 2,e res 2,h res 2,l res 2,(hl) res 2,a res 3,b res 3,c res 3,d res 3,e res 3,h res 3,l res 3,(hl) res 3,a
Ax res 4,b res 4,c res 4,d res 4,e res 4,h res 4,l res 4,(hl) res 4,a res 5,b res 5,c res 5,d res 5,e res 5,h res 5,l res 5,(hl) res 5,a
Bx res 6,b res 6,c res 6,d res 6,e res 6,h res 6,l res 6,(hl) res 6,a res 7,b res 7,c res 7,d res 7,e res 7,h res 7,l res 7,(hl) res 7,a
Cx set 0,b set 0,c set 0,d set 0,e set 0,h set 0,l set 0,(hl) set 0,a set 1,b set 1,c set 1,d set 1,e set 1,h set 1,l set 1,(hl) set 1,a
Dx set 2,b set 2,c set 2,d set 2,e set 2,h set 2,l set 2,(hl) set 2,a set 3,b set 3,c set 3,d set 3,e set 3,h set 3,l set 3,(hl) set 3,a
Ex set 4,b set 4,c set 4,d set 4,e set 4,h set 4,l set 4,(hl) set 4,a set 5,b set 5,c set 5,d set 5,e set 5,h set 5,l set 5,(hl) set 5,a
Fx set 6,b set 6,c set 6,d set 6,e set 6,h set 6,l set 6,(hl) set 6,a set 7,b set 7,c set 7,d set 7,e set 7,h set 7,l set 7,(hl) set 7,a

Operacje z rejestrem IX

\ x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE xF
0x nop ld bc,NN ld (bc),a inc bc inc b dec b ld b,N rlc a ex af,af' add hl,bc ld a,(bc) dec bc inc c dec c ld c,N rrc a
1x djnz X ld de,NN ld (de),a inc de inc d dec d ld d,N rla jr X add hl,de ld a,(de) dec de inc e dec e ld e,N rra
2x jr nz,X ld hl,NN ld (NN),hl inc hl inc h dec h ld h,N daa jr z,X add hl,hl ld hl,(NN) dec hl inc l dec l ld l,N cpl
3x jr nc,X ld sp,NN ld (NN),a inc sp inc (hl) dec (hl) ld (hl),N scf jr c,X add hl,sp ld a,(NN) dec sp inc a dec a ld a,N ccf
4x ld b,b ld b,c ld b,d ld b,e ld b,h ld b,l ld b,(hl) ld b,a ld c,b ld c,c ld c,d ld c,e ld c,h ld c,l ld c,(hl) ld c,a
5x ld d,b ld d,c ld d,d ld d,e ld d,h ld d,l ld d,(hl) ld d,a ld e,b ld e,c ld e,d ld e,e ld e,h ld e,l ld e,(hl) ld e,a
6x ld h,b ld h,c ld h,d ld h,e ld h,h ld h,l ld h,(hl) ld h,a ld l,b ld l,c ld l,d ld l,e ld l,h ld l,l ld l,(hl) ld l,a
7x ld (hl),b ld (hl),c ld (hl),d ld (hl),e ld (hl),h ld (hl),l halt ld (hl),a ld a,b ld a,c ld a,d ld a,e ld a,h ld a,l ld a,(hl) ld a,a
8x add a,b add a,c add a,d add a,e add a,h add a,l add a,(hl) add a,a adc a,b adc a,c adc a,d adc a,e adc a,h adc a,l adc a,(hl) adc a,a
9x sub b sub c sub d sub e sub h sub l sub (hl) sub a sbc a,b sbc a,c sbc a,d sbc a,e sbc a,h sbc a,l sbc a,(hl) sbc a,a
Ax and b and c and d and e and h and l and (hl) and a xor b xor c xor d xor e xor h xor l xor (hl) xor a
Bx or b or c or d or e or h or l or (hl) or a cp b cp c cp d cp e cp h cp l cp (hl) cp a
Cx ret nz pop bc jp nz,NN jp NN call nz,NN push bc add a,N rst 0 ret z ret jp z,NN prefix DDCB call z,NN call NN adc a,N rst 8
Dx ret nc pop de jp nc,NN out (N),a call nc,NN push de sub N rst 16 ret c exx jp c,NN in a,(N) call c,NN   sbc a,N rst 24
Ex ret po pop hl jp po,NN ex (sp),hl call po,NN push hl and N rst 32 ret pe jp (hl) jp pe,NN ex de,hl call pe,NN prefix DDED xor N rst 40
Fx ret p pop af jp p,NN di call p,NN push af or N rst 48 ret m ld sp,hl jp m,NN ei call m,NN   cp N rst 56

Prefix DDCB

\ x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE xF
0x rlc b rlc c rlc d rlc e rlc h rlc l rlc (hl) rlc a rrc b rrc c rrc d rrc e rrc h rrc l rrc (hl) rrc a
1x rl b rl c rl d rl e rl h rl l rl (hl) rl a rr b rr c rr d rr e rr h rr l rr (hl) rr a
2x sla b sla c sla d sla e sla h sla l sla (hl) sla a sra b sra c sra d sra e sra h sra l sra (hl) sra a
3x sll b sll c sll d sll e sll h sll l sll (hl) sll a srl b srl c srl d srl e srl h srl l srl (hl) srl a
4x bit 0,b bit 0,c bit 0,d bit 0,e bit 0,h bit 0,l bit 0,(hl) bit 0,a bit 1,b bit 1,c bit 1,d bit 1,e bit 1,h bit 1,l bit 1,(hl) bit 1,a
5x bit 2,b bit 2,c bit 2,d bit 2,e bit 2,h bit 2,l bit 2,(hl) bit 2,a bit 3,b bit 3,c bit 3,d bit 3,e bit 3,h bit 3,l bit 3,(hl) bit 3,a
6x bit 4,b bit 4,c bit 4,d bit 4,e bit 4,h bit 4,l bit 4,(hl) bit 4,a bit 5,b bit 5,c bit 5,d bit 5,e bit 5,h bit 5,l bit 5,(hl) bit 5,a
7x bit 6,b bit 6,c bit 6,d bit 6,e bit 6,h bit 6,l bit 6,(hl) bit 6,a bit 7,b bit 7,c bit 7,d bit 7,e bit 7,h bit 7,l bit 7,(hl) bit 7,a
8x res 0,b res 0,c res 0,d res 0,e res 0,h res 0,l res 0,(hl) res 0,a res 1,b res 1,c res 1,d res 1,e res 1,h res 1,l res 1,(hl) res 1,a
9x res 2,b res 2,c res 2,d res 2,e res 2,h res 2,l res 2,(hl) res 2,a res 3,b res 3,c res 3,d res 3,e res 3,h res 3,l res 3,(hl) res 3,a
Ax res 4,b res 4,c res 4,d res 4,e res 4,h res 4,l res 4,(hl) res 4,a res 5,b res 5,c res 5,d res 5,e res 5,h res 5,l res 5,(hl) res 5,a
Bx res 6,b res 6,c res 6,d res 6,e res 6,h res 6,l res 6,(hl) res 6,a res 7,b res 7,c res 7,d res 7,e res 7,h res 7,l res 7,(hl) res 7,a
Cx set 0,b set 0,c set 0,d set 0,e set 0,h set 0,l set 0,(hl) set 0,a set 1,b set 1,c set 1,d set 1,e set 1,h set 1,l set 1,(hl) set 1,a
Dx set 2,b set 2,c set 2,d set 2,e set 2,h set 2,l set 2,(hl) set 2,a set 3,b set 3,c set 3,d set 3,e set 3,h set 3,l set 3,(hl) set 3,a
Ex set 4,b set 4,c set 4,d set 4,e set 4,h set 4,l set 4,(hl) set 4,a set 5,b set 5,c set 5,d set 5,e set 5,h set 5,l set 5,(hl) set 5,a
Fx set 6,b set 6,c set 6,d set 6,e set 6,h set 6,l set 6,(hl) set 6,a set 7,b set 7,c set 7,d set 7,e set 7,h set 7,l set 7,(hl) set 7,a

Prefix DDED

\ x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE xF
0x                                
1x                                
2x                                
3x                                
4x in b,(c) out (c),b sbc hl,bc ld (NN),bc neg retn im 0 ld i,a in c,(c) out (c),c adc hl,bc ld bc,(NN)   reti   ld r,a
5x in d,(c) out (c),d sbc hl,de ld (NN),de     im 1 ld a,i in e,(c) out (c),e adc hl,de ld de,(NN)     im 2 ld a,r
6x in h,(c) out (c),h sbc hl,hl ld (NN),hl       rrd in l,(c) out (c),l adc hl,hl ld hl,(NN)       rld
7x in f,(c) out (c),f sbc hl,sp ld (NN),sp         in a,(c) out (c),a adc hl,sp ld sp,(NN)        
8x                                
9x                                
Ax ldi cpi ini outi         ldd cpd ind outd        
Bx ldir cpir inir otir         lddr cpdr indr otdr        
Cx                                
Dx                                
Ex                                
Fx                                

Operacje z rejestrem IY

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