Lista rozkazów - tabela: Różnice pomiędzy wersjami

Wersja z 15:11, 11 cze 2014

Spis treści

1 Podstawowe
2 Prefix CB
3 Prefix ED
4 Prefix DD - Operacje z rejestrem IX
- 4.1 Prefix DDCB
5 Prefix FD - Operacje z rejestrem IY
- 5.1 Prefix FDCB

Podstawowe

\	x0	x1	x2	x3	x4	x5	x6	x7	x8	x9	xA	xB	xC	xD	xE	xF
0x	nop	ld bc,nn	ld (bc),a	inc bc	inc b	dec b	ld b,n	rlca	ex af,af'	add hl,bc	ld a,(bc)	dec bc	inc c	dec c	ld c,n	rrca
1x	djnz u	ld de,nn	ld (de),a	inc de	inc d	dec d	ld d,n	rla	jr u	add hl,de	ld a,(de)	dec de	inc e	dec e	ld e,n	rra
2x	jr nz,u	ld hl,nn	ld (nn),hl	inc hl	inc h	dec h	ld h,n	daa	jr z,u	add hl,hl	ld hl,(nn)	dec hl	inc l	dec l	ld l,n	cpl
3x	jr nc,u	ld sp,nn	ld (nn),a	inc sp	inc (hl)	dec (hl)	ld (hl),n	scf	jr c,u	add hl,sp	ld a,(nn)	dec sp	inc a	dec a	ld a,n	ccf
4x	ld b,b	ld b,c	ld b,d	ld b,e	ld b,h	ld b,l	ld b,(hl)	ld b,a	ld c,b	ld c,c	ld c,d	ld c,e	ld c,h	ld c,l	ld c,(hl)	ld c,a
5x	ld d,b	ld d,c	ld d,d	ld d,e	ld d,h	ld d,l	ld d,(hl)	ld d,a	ld e,b	ld e,c	ld e,d	ld e,e	ld e,h	ld e,l	ld e,(hl)	ld e,a
6x	ld h,b	ld h,c	ld h,d	ld h,e	ld h,h	ld h,l	ld h,(hl)	ld h,a	ld l,b	ld l,c	ld l,d	ld l,e	ld l,h	ld l,l	ld l,(hl)	ld l,a
7x	ld (hl),b	ld (hl),c	ld (hl),d	ld (hl),e	ld (hl),h	ld (hl),l	halt	ld (hl),a	ld a,b	ld a,c	ld a,d	ld a,e	ld a,h	ld a,l	ld a,(hl)	ld a,a
8x	add a,b	add a,c	add a,d	add a,e	add a,h	add a,l	add a,(hl)	add a,a	adc a,b	adc a,c	adc a,d	adc a,e	adc a,h	adc a,l	adc a,(hl)	adc a,a
9x	sub b	sub c	sub d	sub e	sub h	sub l	sub (hl)	sub a	sbc a,b	sbc a,c	sbc a,d	sbc a,e	sbc a,h	sbc a,l	sbc a,(hl)	sbc a,a
Ax	and b	and c	and d	and e	and h	and l	and (hl)	and a	xor b	xor c	xor d	xor e	xor h	xor l	xor (hl)	xor a
Bx	or b	or c	or d	or e	or h	or l	or (hl)	or a	cp b	cp c	cp d	cp e	cp h	cp l	cp (hl)	cp a
Cx	ret nz	pop bc	jp nz,nn	jp nn	call nz,nn	push bc	add a,n	rst 0	ret z	ret	jp z,nn	prefix CB	call z,nn	call nn	adc a,n	rst 8
Dx	ret nc	pop de	jp nc,nn	out (n),a	call nc,nn	push de	sub n	rst 16	ret c	exx	jp c,nn	in a,(n)	call c,nn	prefix DD	sbc a,n	rst 24
Ex	ret po	pop hl	jp po,nn	ex (sp),hl	call po,nn	push hl	and n	rst 32	ret pe	jp (hl)	jp pe,nn	ex de,hl	call pe,nn	prefix ED	xor n	rst 40
Fx	ret p	pop af	jp p,nn	di	call p,nn	push af	or n	rst 48	ret m	ld sp,hl	jp m,nn	ei	call m,nn	prefix FD	cp n	rst 56

Prefix CB

\	x0	x1	x2	x3	x4	x5	x6	x7	x8	x9	xA	xB	xC	xD	xE	xF
0x	rlc b	rlc c	rlc d	rlc e	rlc h	rlc l	rlc (hl)	rlc a	rrc b	rrc c	rrc d	rrc e	rrc h	rrc l	rrc (hl)	rrc a
1x	rl b	rl c	rl d	rl e	rl h	rl l	rl (hl)	rl a	rr b	rr c	rr d	rr e	rr h	rr l	rr (hl)	rr a
2x	sla b	sla c	sla d	sla e	sla h	sla l	sla (hl)	sla a	sra b	sra c	sra d	sra e	sra h	sra l	sra (hl)	sra a
3x	sll b	sll c	sll d	sll e	sll h	sll l	sll (hl)	sll a	srl b	srl c	srl d	srl e	srl h	srl l	srl (hl)	srl a
4x	bit 0,b	bit 0,c	bit 0,d	bit 0,e	bit 0,h	bit 0,l	bit 0,(hl)	bit 0,a	bit 1,b	bit 1,c	bit 1,d	bit 1,e	bit 1,h	bit 1,l	bit 1,(hl)	bit 1,a
5x	bit 2,b	bit 2,c	bit 2,d	bit 2,e	bit 2,h	bit 2,l	bit 2,(hl)	bit 2,a	bit 3,b	bit 3,c	bit 3,d	bit 3,e	bit 3,h	bit 3,l	bit 3,(hl)	bit 3,a
6x	bit 4,b	bit 4,c	bit 4,d	bit 4,e	bit 4,h	bit 4,l	bit 4,(hl)	bit 4,a	bit 5,b	bit 5,c	bit 5,d	bit 5,e	bit 5,h	bit 5,l	bit 5,(hl)	bit 5,a
7x	bit 6,b	bit 6,c	bit 6,d	bit 6,e	bit 6,h	bit 6,l	bit 6,(hl)	bit 6,a	bit 7,b	bit 7,c	bit 7,d	bit 7,e	bit 7,h	bit 7,l	bit 7,(hl)	bit 7,a
8x	res 0,b	res 0,c	res 0,d	res 0,e	res 0,h	res 0,l	res 0,(hl)	res 0,a	res 1,b	res 1,c	res 1,d	res 1,e	res 1,h	res 1,l	res 1,(hl)	res 1,a
9x	res 2,b	res 2,c	res 2,d	res 2,e	res 2,h	res 2,l	res 2,(hl)	res 2,a	res 3,b	res 3,c	res 3,d	res 3,e	res 3,h	res 3,l	res 3,(hl)	res 3,a
Ax	res 4,b	res 4,c	res 4,d	res 4,e	res 4,h	res 4,l	res 4,(hl)	res 4,a	res 5,b	res 5,c	res 5,d	res 5,e	res 5,h	res 5,l	res 5,(hl)	res 5,a
Bx	res 6,b	res 6,c	res 6,d	res 6,e	res 6,h	res 6,l	res 6,(hl)	res 6,a	res 7,b	res 7,c	res 7,d	res 7,e	res 7,h	res 7,l	res 7,(hl)	res 7,a
Cx	set 0,b	set 0,c	set 0,d	set 0,e	set 0,h	set 0,l	set 0,(hl)	set 0,a	set 1,b	set 1,c	set 1,d	set 1,e	set 1,h	set 1,l	set 1,(hl)	set 1,a
Dx	set 2,b	set 2,c	set 2,d	set 2,e	set 2,h	set 2,l	set 2,(hl)	set 2,a	set 3,b	set 3,c	set 3,d	set 3,e	set 3,h	set 3,l	set 3,(hl)	set 3,a
Ex	set 4,b	set 4,c	set 4,d	set 4,e	set 4,h	set 4,l	set 4,(hl)	set 4,a	set 5,b	set 5,c	set 5,d	set 5,e	set 5,h	set 5,l	set 5,(hl)	set 5,a
Fx	set 6,b	set 6,c	set 6,d	set 6,e	set 6,h	set 6,l	set 6,(hl)	set 6,a	set 7,b	set 7,c	set 7,d	set 7,e	set 7,h	set 7,l	set 7,(hl)	set 7,a

Prefix ED

\	x0	x1	x2	x3	x4	x5	x6	x7	x8	x9	xA	xB	xC	xD	xE	xF
0x	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI
1x	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI
2x	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI
3x	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI
4x	in b,(c)	out (c),b	sbc hl,bc	ld (nn),bc	neg	retn	im 0	ld i,a	in c,(c)	out (c),c	adc hl,bc	ld bc,(nn)	neg	reti	im 0	ld r,a
5x	in d,(c)	out (c),d	sbc hl,de	ld (nn),de	neg	retn	im 1	ld a,i	in e,(c)	out (c),e	adc hl,de	ld de,(nn)	neg	retn	im 2	ld a,r
6x	in h,(c)	out (c),h	sbc hl,hl	ld (nn),hl	neg	retn	im 0	rrd	in l,(c)	out (c),l	adc hl,hl	ld hl,(nn)	neg	retn	im 0	rld
7x	in f,(c)	out (c),0	sbc hl,sp	ld (nn),sp	neg	retn	im 1	NONI	in a,(c)	out (c),a	adc hl,sp	ld sp,(nn)	neg	retn	im 2	NONI
8x	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI
9x	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI
Ax	ldi	cpi	ini	outi	NONI	NONI	NONI	NONI	ldd	cpd	ind	outd	NONI	NONI	NONI	NONI
Bx	ldir	cpir	inir	otir	NONI	NONI	NONI	NONI	lddr	cpdr	indr	otdr	NONI	NONI	NONI	NONI
Cx	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI
Dx	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI
Ex	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI
Fx	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI	NONI

Prefix DD - Operacje z rejestrem IX

\	x0	x1	x2	x3	x4	x5	x6	x7	x8	x9	xA	xB	xC	xD	xE	xF
0x										add ix,bc
1x										add ix,de
2x		ld ix,nn	ld (nn),ix	inc ix	inc ixh	dec ixh	ld ixh,n			add ix,ix	ld ix,(nn)	dec ix	inc ixl	dec ixl	ld ixl,n
3x					inc (ix+u)	dec (ix+u)				add ix,sp
4x					ld b,ixh	ld b,ixl	ld b,(ix+u)						ld c,ixh	ld c,ixl	ld c,(ix+u)
5x					ld d,ixh	ld d,ixl	ld d,(ix+u)						ld e,ixh	ld e,ixl	ld e,(ix+u)
6x	ld ixh,b	ld ixh,c	ld ixh,d	ld ixh,e	ld ixh,ixh	ld ixh,ixl	ld h,(ix+u)	ld ixh,a	ld ixl,b	ld ixl,c	ld ixl,d	ld ixl,e	ld ixl,ixh	ld ixl,ixl	ld l,(ix+u)	ld ixl,a
7x	ld (ix+u),b	ld (ix+u),c	ld (ix+u),d	ld (ix+u),e	ld (ix+u),h	ld (ix+u),l		ld (ix+u),a					ld a,ixh	ld a,ixl	ld a,(ix+u)
8x					add a,ixh	add a,ixl	add a,(ix+u)						adc a,ixh	adc a,ixl	adc a,(ix+u)
9x					sub a,ixh	sub a,ixl	sub (ix+u)						sbc a,ixh	sbc a,ixl	sbc a,(ix+u)
Ax					and ixh	and ixl	and (ix+u)						xor ixh	xor ixl	xor (ix+u)
Bx					or ixh	or ixl	or (ix+u)						cp ixh	cp ixl	cp (ix+u)
Cx												prefix DDCB
Dx
Ex		pop ix		ex (sp),ix		push ix				jp (ix)
Fx										ld sp,ix

Prefix DDCB

\	x0	x1	x2	x3	x4	x5	x6	x7	x8	x9	xA	xB	xC	xD	xE	xF
0x	rlc (ix+u),b	rlc (ix+u),c	rlc (ix+u),d	rlc (ix+u),e	rlc (ix+u),h	rlc (ix+u),l	rlc (ix+u)	rlc (ix+u),a	rrc (ix+u),b	rrc (ix+u),c	rrc (ix+u),d	rrc (ix+u),e	rrc (ix+u),h	rrc (ix+u),l	rrc (ix+u)	rrc (ix+u),a
1x	rl (ix+u),b	rl (ix+u),c	rl (ix+u),d	rl (ix+u),e	rl (ix+u),h	rl (ix+u),l	rl (ix+u)	rl (ix+u),a	rr (ix+u),b	rr (ix+u),c	rr (ix+u),d	rr (ix+u),e	rr (ix+u),h	rr (ix+u),l	rr (ix+u)	rr (ix+u),a
2x	sla (ix+u),b	sla (ix+u),c	sla (ix+u),d	sla (ix+u),e	sla (ix+u),h	sla (ix+u),l	sla (ix+u)	sla (ix+u),a	sra (ix+u),b	sra (ix+u),c	sra (ix+u),d	sra (ix+u),e	sra (ix+u),h	sra (ix+u),l	sra (ix+u)	sra (ix+u),a
3x	sll (ix+u),b	sll (ix+u),c	sll (ix+u),d	sll (ix+u),e	sll (ix+u),h	sll (ix+u),l	sll (ix+u)	sll (ix+u),a	srl (ix+u),b	srl (ix+u),c	srl (ix+u),d	srl (ix+u),e	srl (ix+u),h	srl (ix+u),l	srl (ix+u)	srl (ix+u),a
4x	bit 0,(ix+u)	bit 0,(ix+u)	bit 0,(ix+u)	bit 0,(ix+u)	bit 0,(ix+u)	bit 0,(ix+u)	bit 0,(ix+u)	bit 0,(ix+u)	bit 1,(ix+u)	bit 1,(ix+u)	bit 1,(ix+u)	bit 1,(ix+u)	bit 1,(ix+u)	bit 1,(ix+u)	bit 1,(ix+u)	bit 1,(ix+u)
5x	bit 2,(ix+u)	bit 2,(ix+u)	bit 2,(ix+u)	bit 2,(ix+u)	bit 2,(ix+u)	bit 2,(ix+u)	bit 2,(ix+u)	bit 2,(ix+u)	bit 3,(ix+u)	bit 3,(ix+u)	bit 3,(ix+u)	bit 3,(ix+u)	bit 3,(ix+u)	bit 3,(ix+u)	bit 3,(ix+u)	bit 3,(ix+u)
6x	bit 4,(ix+u)	bit 4,(ix+u)	bit 4,(ix+u)	bit 4,(ix+u)	bit 4,(ix+u)	bit 4,(ix+u)	bit 4,(ix+u)	bit 4,(ix+u)	bit 5,(ix+u)	bit 5,(ix+u)	bit 5,(ix+u)	bit 5,(ix+u)	bit 5,(ix+u)	bit 5,(ix+u)	bit 5,(ix+u)	bit 5,(ix+u)
7x	bit 6,(ix+u)	bit 6,(ix+u)	bit 6,(ix+u)	bit 6,(ix+u)	bit 6,(ix+u)	bit 6,(ix+u)	bit 6,(ix+u)	bit 6,(ix+u)	bit 7,(ix+u)	bit 7,(ix+u)	bit 7,(ix+u)	bit 7,(ix+u)	bit 7,(ix+u)	bit 7,(ix+u)	bit 7,(ix+u)	bit 7,(ix+u)
8x	res 0,(ix+u),b	res 0,(ix+u),c	res 0,(ix+u),d	res 0,(ix+u),e	res 0,(ix+u),h	res 0,(ix+u),l	res 0,(ix+u)	res 0,(ix+u),a	res 1,(ix+u),b	res 1,(ix+u),c	res 1,(ix+u),d	res 1,(ix+u),e	res 1,(ix+u),h	res 1,(ix+u),l	res 1,(ix+u)	res 1,(ix+u),a
9x	res 2,(ix+u),b	res 2,(ix+u),c	res 2,(ix+u),d	res 2,(ix+u),e	res 2,(ix+u),h	res 2,(ix+u),l	res 2,(ix+u)	res 2,(ix+u),a	res 3,(ix+u),b	res 3,(ix+u),c	res 3,(ix+u),d	res 3,(ix+u),e	res 3,(ix+u),h	res 3,(ix+u),l	res 3,(ix+u)	res 3,(ix+u),a
Ax	res 4,(ix+u),b	res 4,(ix+u),c	res 4,(ix+u),d	res 4,(ix+u),e	res 4,(ix+u),h	res 4,(ix+u),l	res 4,(ix+u)	res 4,(ix+u),a	res 5,(ix+u),b	res 5,(ix+u),c	res 5,(ix+u),d	res 5,(ix+u),e	res 5,(ix+u),h	res 5,(ix+u),l	res 5,(ix+u)	res 5,(ix+u),a
Bx	res 6,(ix+u),b	res 6,(ix+u),c	res 6,(ix+u),d	res 6,(ix+u),e	res 6,(ix+u),h	res 6,(ix+u),l	res 6,(ix+u)	res 6,(ix+u),a	res 7,(ix+u),b	res 7,(ix+u),c	res 7,(ix+u),d	res 7,(ix+u),e	res 7,(ix+u),h	res 7,(ix+u),l	res 7,(ix+u)	res 7,(ix+u),a
Cx	set 0,(ix+u),b	set 0,(ix+u),c	set 0,(ix+u),d	set 0,(ix+u),e	set 0,(ix+u),h	set 0,(ix+u),l	set 0,(ix+u)	set 0,(ix+u),a	set 1,(ix+u),b	set 1,(ix+u),c	set 1,(ix+u),d	set 1,(ix+u),e	set 1,(ix+u),h	set 1,(ix+u),l	set 1,(ix+u)	set 1,(ix+u),a
Dx	set 2,(ix+u),b	set 2,(ix+u),c	set 2,(ix+u),d	set 2,(ix+u),e	set 2,(ix+u),h	set 2,(ix+u),l	set 2,(ix+u)	set 2,(ix+u),a	set 3,(ix+u),b	set 3,(ix+u),c	set 3,(ix+u),d	set 3,(ix+u),e	set 3,(ix+u),h	set 3,(ix+u),l	set 3,(ix+u)	set 3,(ix+u),a
Ex	set 4,(ix+u),b	set 4,(ix+u),c	set 4,(ix+u),d	set 4,(ix+u),e	set 4,(ix+u),h	set 4,(ix+u),l	set 4,(ix+u)	set 4,(ix+u),a	set 5,(ix+u),b	set 5,(ix+u),c	set 5,(ix+u),d	set 5,(ix+u),e	set 5,(ix+u),h	set 5,(ix+u),l	set 5,(ix+u)	set 5,(ix+u),a
Fx	set 6,(ix+u),b	set 6,(ix+u),c	set 6,(ix+u),d	set 6,(ix+u),e	set 6,(ix+u),h	set 6,(ix+u),l	set 6,(ix+u)	set 6,(ix+u),a	set 7,(ix+u),b	set 7,(ix+u),c	set 7,(ix+u),d	set 7,(ix+u),e	set 7,(ix+u),h	set 7,(ix+u),l	set 7,(ix+u)	set 7,(ix+u),a

Prefix FD - Operacje z rejestrem IY

\	x0	x1	x2	x3	x4	x5	x6	x7	x9	xA	xB	xC	xD	xE
0x									add iy,bc
1x									add iy,de
2x		ld iy,nn	ld (nn),iy	inc iy	inc iyh	dec iyh	ld iyh,n		add iy,iy	ld iy,(nn)	dec iy	inc iyl	dec iyl	ld iyl,n
3x					inc (iy+u)	dec (iy+u)			add iy,sp
4x					ld b,iyh	ld b,iyl	ld b,(iy+u)					ld c,iyh	ld c,iyl	ld c,(iy+u)
5x					ld d,iyh	ld d,iyl	ld d,(iy+u)					ld e,iyh	ld e,iyl	ld e,(iy+u)
6x							ld h,(iy+u)							ld l,(iy+u)
7x	ld (iy+u),b	ld (iy+u),c	ld (iy+u),d	ld (iy+u),e	ld (iy+u),h	ld (iy+u),l		ld (iy+u),a				ld a,iyh	ld a,iyl	ld a,(iy+u)
8x					add a,iyh	add a,iyl	add a,(iy+u)					adc a,iyh	adc a,iyl	adc a,(iy+u)
9x					sub iyh	sub iyl	sub (iy+u)					sbc a,iyh	sbc a,iyl	sbc a,(iy+u)
Ax					and iyh	and iyl	and (iy+u)					xor iyh	xor iyl	xor (iy+u)
Bx					or iyh	or iyl	or (iy+u)					cp iyh	cp iyl	cp (iy+u)
Cx											prefix FDCB
Dx
Ex		pop iy		ex (sp),iy		push iy			jp (iy)
Fx									ld sp,iy

Prefix FDCB

\	x0	x1	x2	x3	x4	x5	x6	x7	x8	x9	xA	xB	xC	xD	xE	xF
0x	rlc (iy+u),b	rlc (iy+u),c	rlc (iy+u),d	rlc (iy+u),e	rlc (iy+u),h	rlc (iy+u),l	rlc (iy+u)	rlc (iy+u),a	rrc (iy+u),b	rrc (iy+u),c	rrc (iy+u),d	rrc (iy+u),e	rrc (iy+u),h	rrc (iy+u),l	rrc (iy+u)	rrc (iy+u),a
1x	rl (iy+u),b	rl (iy+u),c	rl (iy+u),d	rl (iy+u),e	rl (iy+u),h	rl (iy+u),l	rl (iy+u)	rl (iy+u),a	rr (iy+u),b	rr (iy+u),c	rr (iy+u),d	rr (iy+u),e	rr (iy+u),h	rr (iy+u),l	rr (iy+u)	rr (iy+u),a
2x	sla (iy+u),b	sla (iy+u),c	sla (iy+u),d	sla (iy+u),e	sla (iy+u),h	sla (iy+u),l	sla (iy+u)	sla (iy+u),a	sra (iy+u),b	sra (iy+u),c	sra (iy+u),d	sra (iy+u),e	sra (iy+u),h	sra (iy+u),l	sra (iy+u)	sra (iy+u),a
3x	sll (iy+u),b	sll (iy+u),c	sll (iy+u),d	sll (iy+u),e	sll (iy+u),h	sll (iy+u),l	sll (iy+u)	sll (iy+u),a	srl (iy+u),b	srl (iy+u),c	srl (iy+u),d	srl (iy+u),e	srl (iy+u),h	srl (iy+u),l	srl (iy+u)	srl (iy+u),a
4x	bit 0,(iy+u)	bit 0,(iy+u)	bit 0,(iy+u)	bit 0,(iy+u)	bit 0,(iy+u)	bit 0,(iy+u)	bit 0,(iy+u)	bit 0,(iy+u)	bit 1,(iy+u)	bit 1,(iy+u)	bit 1,(iy+u)	bit 1,(iy+u)	bit 1,(iy+u)	bit 1,(iy+u)	bit 1,(iy+u)	bit 1,(iy+u)
5x	bit 2,(iy+u)	bit 2,(iy+u)	bit 2,(iy+u)	bit 2,(iy+u)	bit 2,(iy+u)	bit 2,(iy+u)	bit 2,(iy+u)	bit 2,(iy+u)	bit 3,(iy+u)	bit 3,(iy+u)	bit 3,(iy+u)	bit 3,(iy+u)	bit 3,(iy+u)	bit 3,(iy+u)	bit 3,(iy+u)	bit 3,(iy+u)
6x	bit 4,(iy+u)	bit 4,(iy+u)	bit 4,(iy+u)	bit 4,(iy+u)	bit 4,(iy+u)	bit 4,(iy+u)	bit 4,(iy+u)	bit 4,(iy+u)	bit 5,(iy+u)	bit 5,(iy+u)	bit 5,(iy+u)	bit 5,(iy+u)	bit 5,(iy+u)	bit 5,(iy+u)	bit 5,(iy+u)	bit 5,(iy+u)
7x	bit 6,(iy+u)	bit 6,(iy+u)	bit 6,(iy+u)	bit 6,(iy+u)	bit 6,(iy+u)	bit 6,(iy+u)	bit 6,(iy+u)	bit 6,(iy+u)	bit 7,(iy+u)	bit 7,(iy+u)	bit 7,(iy+u)	bit 7,(iy+u)	bit 7,(iy+u)	bit 7,(iy+u)	bit 7,(iy+u)	bit 7,(iy+u)
8x	res 0,(iy+u),b	res 0,(iy+u),c	res 0,(iy+u),d	res 0,(iy+u),e	res 0,(iy+u),h	res 0,(iy+u),l	res 0,(iy+u)	res 0,(iy+u),a	res 1,(iy+u),b	res 1,(iy+u),c	res 1,(iy+u),d	res 1,(iy+u),e	res 1,(iy+u),h	res 1,(iy+u),l	res 1,(iy+u)	res 1,(iy+u),a
9x	res 2,(iy+u),b	res 2,(iy+u),c	res 2,(iy+u),d	res 2,(iy+u),e	res 2,(iy+u),h	res 2,(iy+u),l	res 2,(iy+u)	res 2,(iy+u),a	res 3,(iy+u),b	res 3,(iy+u),c	res 3,(iy+u),d	res 3,(iy+u),e	res 3,(iy+u),h	res 3,(iy+u),l	res 3,(iy+u)	res 3,(iy+u),a
Ax	res 4,(iy+u),b	res 4,(iy+u),c	res 4,(iy+u),d	res 4,(iy+u),e	res 4,(iy+u),h	res 4,(iy+u),l	res 4,(iy+u)	res 4,(iy+u),a	res 5,(iy+u),b	res 5,(iy+u),c	res 5,(iy+u),d	res 5,(iy+u),e	res 5,(iy+u),h	res 5,(iy+u),l	res 5,(iy+u)	res 5,(iy+u),a
Bx	res 6,(iy+u),b	res 6,(iy+u),c	res 6,(iy+u),d	res 6,(iy+u),e	res 6,(iy+u),h	res 6,(iy+u),l	res 6,(iy+u)	res 6,(iy+u),a	res 7,(iy+u),b	res 7,(iy+u),c	res 7,(iy+u),d	res 7,(iy+u),e	res 7,(iy+u),h	res 7,(iy+u),l	res 7,(iy+u)	res 7,(iy+u),a
Cx	set 0,(iy+u),b	set 0,(iy+u),c	set 0,(iy+u),d	set 0,(iy+u),e	set 0,(iy+u),h	set 0,(iy+u),l	set 0,(iy+u)	set 0,(iy+u),a	set 1,(iy+u),b	set 1,(iy+u),c	set 1,(iy+u),d	set 1,(iy+u),e	set 1,(iy+u),h	set 1,(iy+u),l	set 1,(iy+u)	set 1,(iy+u),a
Dx	set 2,(iy+u),b	set 2,(iy+u),c	set 2,(iy+u),d	set 2,(iy+u),e	set 2,(iy+u),h	set 2,(iy+u),l	set 2,(iy+u)	set 2,(iy+u),a	set 3,(iy+u),b	set 3,(iy+u),c	set 3,(iy+u),d	set 3,(iy+u),e	set 3,(iy+u),h	set 3,(iy+u),l	set 3,(iy+u)	set 3,(iy+u),a
Ex	set 4,(iy+u),b	set 4,(iy+u),c	set 4,(iy+u),d	set 4,(iy+u),e	set 4,(iy+u),h	set 4,(iy+u),l	set 4,(iy+u)	set 4,(iy+u),a	set 5,(iy+u),b	set 5,(iy+u),c	set 5,(iy+u),d	set 5,(iy+u),e	set 5,(iy+u),h	set 5,(iy+u),l	set 5,(iy+u)	set 5,(iy+u),a
Fx	set 6,(iy+u),b	set 6,(iy+u),c	set 6,(iy+u),d	set 6,(iy+u),e	set 6,(iy+u),h	set 6,(iy+u),l	set 6,(iy+u)	set 6,(iy+u),a	set 7,(iy+u),b	set 7,(iy+u),c	set 7,(iy+u),d	set 7,(iy+u),e	set 7,(iy+u),h	set 7,(iy+u),l	set 7,(iy+u)	set 7,(iy+u),a

@@ Linia 988: / Linia 988: @@
 |[[Rozkaz LD|ld (nn),ix]]
 |[[Rozkaz INC|inc ix]]
-|<i>inc ixh</i>
+|style="background-color: lightgray"|<i>[[Rozkaz INC#Nieudokumentowane|inc ixh]]</i>
-|<i>dec ixh</i>
+|style="background-color: lightgray"|<i>[[Rozkaz DEC#Nieudokumentowane|dec ixh]]</i>
-|<i>ld ixh,n</i>
+|style="background-color: lightgray"|<i>[[Rozkaz LD#Nieudokumentowane|ld ixh,n]]</i>
 |&nbsp;
 |&nbsp;
@@ Linia 996: / Linia 996: @@
 |[[Rozkaz LD|ld ix,(nn)]]
 |[[Rozkaz DEC|dec ix]]
-|<i>inc ixl</i>
+|style="background-color: lightgray"|<i>[[Rozkaz INC#Nieudokumentowane|inc ixl]]</i>
-|<i>dec ixl</i>
+|style="background-color: lightgray"|<i>[[Rozkaz DEC#Nieudokumentowane|dec ixl]]</i>
-|<i>ld ixl,n</i>
+|style="background-color: lightgray"|<i>[[Rozkaz LD#Nieudokumentowane|ld ixl,n]]</i>
 |&nbsp;
 |-
@@ Linia 1024: / Linia 1024: @@
 |&nbsp;
 |&nbsp;
-|<i>ld b,ixh</i>
+|style="background-color: lightgray"|<i>[[Rozkaz LD#Nieudokumentowane|ld b,ixh]]</i>
-|<i>ld b,ixl</i>
+|style="background-color: lightgray"|<i>[[Rozkaz LD#Nieudokumentowane|ld b,ixl]]</i>
 |[[Rozkaz LD|ld b,(ix+u)]]
 |&nbsp;
@@ Linia 1032: / Linia 1032: @@
 |&nbsp;
 |&nbsp;
-|<i>ld c,ixh</i>
+|style="background-color: lightgray"|<i>[[Rozkaz LD#Nieudokumentowane|ld c,ixh]]</i>
-|<i>ld c,ixl</i>
+|style="background-color: lightgray"|<i>[[Rozkaz LD#Nieudokumentowane|ld c,ixl]]</i>
 |[[Rozkaz LD|ld c,(ix+u)]]
 |&nbsp;
@@ Linia 1042: / Linia 1042: @@
 |&nbsp;
 |&nbsp;
-|<i>ld d,ixh</i>
+|style="background-color: lightgray"|<i>[[Rozkaz LD#Nieudokumentowane|ld d,ixh]]</i>
-|<i>ld d,ixl</i>
+|style="background-color: lightgray"|<i>[[Rozkaz LD#Nieudokumentowane|ld d,ixl]]</i>
 |[[Rozkaz LD|ld d,(ix+u)]]
 |&nbsp;
@@ Linia 1050: / Linia 1050: @@
 |&nbsp;
 |&nbsp;
-|<i>ld e,ixh</i>
+|style="background-color: lightgray"|<i>[[Rozkaz LD#Nieudokumentowane|ld e,ixh]]</i>
-|<i>ld e,ixl</i>
+|style="background-color: lightgray"|<i>[[Rozkaz LD#Nieudokumentowane|ld e,ixl]]</i>
 |[[Rozkaz LD|ld e,(ix+u)]]
 |&nbsp;
 |-
 !scope="row"|6x
-|&nbsp;
+|style="background-color: lightgray"|<i>[[Rozkaz LD#Nieudokumentowane|ld ixh,b]]</i>
-|&nbsp;
+|style="background-color: lightgray"|<i>[[Rozkaz LD#Nieudokumentowane|ld ixh,c]]</i>
-|&nbsp;
+|style="background-color: lightgray"|<i>[[Rozkaz LD#Nieudokumentowane|ld ixh,d]]</i>
-|&nbsp;
+|style="background-color: lightgray"|<i>[[Rozkaz LD#Nieudokumentowane|ld ixh,e]]</i>
-|&nbsp;
+|style="background-color: lightgray"|<i>[[Rozkaz LD#Nieudokumentowane|ld ixh,ixh]]</i>
-|&nbsp;
+|style="background-color: lightgray"|<i>[[Rozkaz LD#Nieudokumentowane|ld ixh,ixl]]</i>
 |[[Rozkaz LD|ld h,(ix+u)]]
-|&nbsp;
+|style="background-color: lightgray"|<i>[[Rozkaz LD#Nieudokumentowane|ld ixh,a]]</i>
-|&nbsp;
+|style="background-color: lightgray"|<i>[[Rozkaz LD#Nieudokumentowane|ld ixl,b]]</i>
-|&nbsp;
+|style="background-color: lightgray"|<i>[[Rozkaz LD#Nieudokumentowane|ld ixl,c]]</i>
-|&nbsp;
+|style="background-color: lightgray"|<i>[[Rozkaz LD#Nieudokumentowane|ld ixl,d]]</i>
-|&nbsp;
+|style="background-color: lightgray"|<i>[[Rozkaz LD#Nieudokumentowane|ld ixl,e]]</i>
-|&nbsp;
+|style="background-color: lightgray"|<i>[[Rozkaz LD#Nieudokumentowane|ld ixl,ixh]]</i>
-|&nbsp;
+|style="background-color: lightgray"|<i>[[Rozkaz LD#Nieudokumentowane|ld ixl,ixl]]</i>
 |[[Rozkaz LD|ld l,(ix+u)]]
-|&nbsp;
+|style="background-color: lightgray"|<i>[[Rozkaz LD#Nieudokumentowane|ld ixl,a]]</i>
 |-
 !scope="row"|7x
@@ Linia 1086: / Linia 1086: @@
 |&nbsp;
 |&nbsp;
-|<i>ld a,ixh</i>
+|style="background-color: lightgray"|<i>[[Rozkaz LD#Nieudokumentowane|ld a,ixh]]</i>
-|<i>ld a,ixl</i>
+|style="background-color: lightgray"|<i>[[Rozkaz LD#Nieudokumentowane|ld a,ixl]]</i>
 |[[Rozkaz LD|ld a,(ix+u)]]
 |&nbsp;
@@ Linia 1096: / Linia 1096: @@
 |&nbsp;
 |&nbsp;
-|<i>add a,ixh</i>
+|style="background-color: lightgray"|<i>[[Rozkaz ADD#Nieudokumentowane|add a,ixh]]</i>
-|<i>add a,ixl</i>
+|style="background-color: lightgray"|<i>[[Rozkaz ADD#Nieudokumentowane|add a,ixl]]</i>
 |[[Rozkaz ADD|add a,(ix+u)]]
 |&nbsp;
@@ Linia 1104: / Linia 1104: @@
 |&nbsp;
 |&nbsp;
-|<i>adc a,ixh</i>
+|style="background-color: lightgray"|<i>[[Rozkaz ADC#Nieudokumentowane|adc a,ixh]]</i>
-|<i>adc a,ixl</i>
+|style="background-color: lightgray"|<i>[[Rozkaz ADC#Nieudokumentowane|adc a,ixl]]</i>
 |[[Rozkaz ADC|adc a,(ix+u)]]
 |&nbsp;
@@ Linia 1114: / Linia 1114: @@
 |&nbsp;
 |&nbsp;
-|<i>sub ixh</i>
+|style="background-color: lightgray"|<i>[[Rozkaz SUB#Nieudokumentowane|sub a,ixh]]</i>
-|<i>sub ixl</i>
+|style="background-color: lightgray"|<i>[[Rozkaz SUB#Nieudokumentowane|sub a,ixl]]</i>
 |[[Rozkaz SUB|sub (ix+u)]]
 |&nbsp;
@@ Linia 1122: / Linia 1122: @@
 |&nbsp;
 |&nbsp;
-|<i>sbc a,ixh</i>
+|style="background-color: lightgray"|<i>[[Rozkaz SBC#Nieudokumentowane|sbc a,ixh]]</i>
-|<i>sbc a,ixl</i>
+|style="background-color: lightgray"|<i>[[Rozkaz SBC#Nieudokumentowane|sbc a,ixl]]</i>
 |[[Rozkaz SBC|sbc a,(ix+u)]]
 |&nbsp;
@@ Linia 1132: / Linia 1132: @@
 |&nbsp;
 |&nbsp;
-|<i>and ixh</i>
+|style="background-color: lightgray"|<i>[[Rozkaz AND#Nieudokumentowane|and ixh]]</i>
-|<i>and ixl</i>
+|style="background-color: lightgray"|<i>[[Rozkaz AND#Nieudokumentowane|and ixl]]</i>
 |[[Rozkaz AND|and (ix+u)]]
 |&nbsp;
@@ Linia 1140: / Linia 1140: @@
 |&nbsp;
 |&nbsp;
-|<i>xor ixh</i>
+|style="background-color: lightgray"|<i>[[Rozkaz XOR#Nieudokumentowane|xor ixh]]</i>
-|<i>xor ixl</i>
+|style="background-color: lightgray"|<i>[[Rozkaz XOR#Nieudokumentowane|xor ixl]]</i>
 |[[Rozkaz XOR|xor (ix+u)]]
 |&nbsp;
@@ Linia 1150: / Linia 1150: @@
 |&nbsp;
 |&nbsp;
-|<i>or ixh</i>
+|style="background-color: lightgray"|<i>[[Rozkaz OR#Nieudokumentowane|or ixh]]</i>
-|<i>or ixl</i>
+|style="background-color: lightgray"|<i>[[Rozkaz OR#Nieudokumentowane|or ixl]]</i>
 |[[Rozkaz OR|or (ix+u)]]
 |&nbsp;
@@ Linia 1158: / Linia 1158: @@
 |&nbsp;
 |&nbsp;
-|<i>cp ixh</i>
+|style="background-color: lightgray"|<i>[[Rozkaz CP#Nieudokumentowane|cp ixh]]</i>
-|<i>cp ixl</i>
+|style="background-color: lightgray"|<i>[[Rozkaz CP#Nieudokumentowane|cp ixl]]</i>
 |[[Rozkaz CP|cp (ix+u)]]
 |&nbsp;

Lista rozkazów - tabela: Różnice pomiędzy wersjami

Wersja z 15:11, 11 cze 2014

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Prefix DD - Operacje z rejestrem IX

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